1. Field of the Invention
The present invention is related to a peak current mode control power converter circuit, and more particularly a slope compensation method and circuit used to the peak current control mode power converter circuit that restrains switching noises when the peak current control mode power converter circuit is operating.
2. Description of the Related Art
A conventional DC (direct current) to DC power converter converts a DC power source into one or multiple DC power sources of different voltages, so as to output the DC power sources to corresponding circuit units on a circuit board or corresponding electronic devices.
The DC to DC power converter has different control methods. One controlled method is a peak current. The peak current control mode power converter circuit has an advantage of simplified circuits, but has a drawback of poor noise control ability. With reference to FIG. 8, a conventional DC to DC converter circuit 50 with a peak current controlled mode has a first forward converter 51, a second forward converter 52, and a pulse width modulation (PWM) controller 53.
The first forward converter 51 and the second forward converter 52 have at least two sets of high frequency transformers T3 and T4 and two primary switches Q1 and Q2. Primary sides of the high frequency transformers T3 and T4 are coupled to the corresponding primary switches Q1 and Q2. The primary switches Q1 and Q2 are open or closed to determine whether the primary sides generate currents or not. On the other hand, secondary sides of the high frequency transformers T3 and T4 are output terminals of the DC to DC converter circuit 50 with the peak current.
The PWM controller 53 has a first PWM output terminal OUT1 and a second PWM output terminal OUT2, a first output voltage feedback terminal COMP1 and a second output voltage feedback terminal COMP2, and a first current feedback input terminal CS1 and a second current feedback input terminal CS2. The two PWM output terminals OUT1 and OUT2 are coupled to control terminals of the primary switches Q1 and Q2 of the first forward converter 51 and the second forward converter 52.
The two output voltage feedback terminals COMP1 and COMP2 are coupled to corresponding DC output terminals of the first forward converter 51 and the second forward converter 52, so as to acquire two corresponding voltage feedback signals Verror1 and Verror2 of the two DC output terminals. Moreover, the current feedback input terminals CS1 and CS2 acquire current feedback signals of the primary sides of the corresponding high frequency transformers T3 and T4.
The DC to DC converter circuit 50 modulates a pulse width of each output signal by a peak current mode control method. With further reference to FIG. 9, when the two primary switches Q1 and Q2 are alternatively driven by a pulse width signal of 50% duty cycle, an optimal waveform of current feedback signals of measured currents of the two current feedback input terminals CS1 and CS2 is shown. When the first primary switch Q1 is conductive for a 50% duty cycle time period, a corresponding voltage value VCS1 of a feedback current is larger than a voltage value VCOMP1 of a first voltage feedback signal at an input terminal COMP1.
At this moment, the PWM controller 53 turns off the first primary switch Q1 and also simultaneously controls the second primary switch Q2 to be conductive. With the same manner, when the second primary switch Q2 is conductive for a 50% duty cycle time period, the PWM controller 53 compares a corresponding voltage value VCS2 of the second current feedback input terminal CS2 with a target value VCOMP2 of a second voltage feedback signal at an input terminal COMP2. When the corresponding voltage value VCS2 of a feedback current is larger than the voltage value VCOMP2 of the second voltage feedback signal, the PWM controller 53 turns off the second primary switch Q2 and also simultaneously controls the first primary switch Q1.
Therefore, the PWM controller 53 detects the corresponding voltage values Vcs1 and Vcs2 at the first and second current feedback input terminal CS1 and CS2 in accordance with the current of the primary sides of the high frequency transformers T3 and T4, and then to compare with the voltage values Vcomp1 and Vcomp2 of the voltage feedback signals at the two input terminal COMP1 and COMP2 respectively coupled to the secondary sides of the high frequency transformers T3 and T4. Once the voltage peak value of the voltage value Vcs1 or the voltage value Vcs2 is larger than the feedback voltage value, the PWM controller 53 alternatively changes on and off statuses of the two primary switches Q1 and Q2.
However, when the two primary switches Q1 and Q2 are respectively driven by a pulse width signal of larger than 50% duty cycle, the peak current control mode method is inferior to the aforesaid example. With further reference to FIG. 10, the two primary switches Q1 and Q2 are alternatively driven by a pulse width signal of 55% duty cycle as a target value. When only the first primary switch Q1 is driven to be conductive at t10, the primary switch Q1 should be turned off when a time point t12 reaches the target value in theory. However, a time point t20 is ahead of the time point of t12 of the target value, so that the second 9 primary switch Q2 is conductive. Since the second primary switch Q2 is driven to be conductive at the time point t20, a current waveform of the first current feedback input terminal CS1 produces a surge at a time point t11.
The surge makes the PWM controller 53 determine that a corresponding voltage peak value VCS1 of a first current feedback signal is larger than a voltage value VCOMP1 of a secondary side feedback voltage signal. Hence the primary switch Q1 is turned off at a time point t11. The optimal waveform is shown as a marked dotted line, and the primary switch Q1 is turned off earlier before the target value reaches. With further reference to FIG. 11, an output DC power of the first high frequency transformer T3 and the second high frequency transformer T4 can not avoid generating oscillation.
Similarly, when the second primary switch Q2 is conductive for 55% duty cycle t20 to t211, the primary switch Q1 is driven to be conductive again by the PWM controller 53 at a time point t13. At the time point t13 the coupling effect is generated, so as to influence the primary side current of the second conductive high frequency transformer T4 to produce a surge. Hence a corresponding voltage peak value VCS2 of a second current feedback signal is larger than a voltage value VCOMP2 of a second voltage feedback signal at a time point t21 before the time point t211 of the target value, so as to turn off the second primary switch Q2. In comparison with the optimal waveform as the dotted line, the second primary switch Q2 is turned off earlier. Nevertheless, the DC power oscillation is still generated.
Therefore, it can be clearly understood that when the PWM signals of the two primary switches Q1 and Q2 are larger than 50% duty cycle, operation periods of the first forward converter 51 and the second forward converter 52 become overlapped. At this moment, the turned off primary switch generates a noise and the noise is coupling to the other current waveform, so as to influence the peak current and further result in an output oscillation phenomenon. Thereby the conventional DC to DC converter has to be further improved to provide more stable DC power supply.